Format |
Syntax: |
Operation: |
Operands: |
Architecture revision |
Opcode | ||||||||||||
1 |
plsr.b Rd, Rs, sa |
Rd[31:24] = LSR(Rs[31:24], sa3); Rd[23:16] = LSR(Rs[23:16], sa3); Rd[15:8] = LSR(Rs[15:8], sa3); Rd[7:0] = LSR(Rs[7:0], sa3); |
{d, s} ∈ {0, 1, …, 15} |
Rev1+ |
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2 |
plsr.h Rd, Rs, sa |
Rd[31:16] = LSR(Rs[31:16], sa4); Rd[15:0] = LSR(Rs[15:0], sa4); |
{d, s} ∈ {0, 1, …, 15} |
Rev1+ |
|
Perform a logical shift right on each of the packed bytes or halfwords in the source register and store the result to the destination register.
Q: |
Not affected. |
V: |
Not affected. |
N: |
Not affected. |
Z: |
Not affected. |
C: |
Not affected. |